View MP2953BGU-0000-Z_8904226.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

mp2953b digital multi-phase controller with pmbus interface for vr12.5 mp2953b rev. 1.01 www.monolithicpower.com 1 10/9/2015 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2015 mps. all rights reserved. the future of analog ic technology description the mp2953b is a digital multi-phase controller that provides power for the core of the intel vr12.5 platform. it works with mps? intelli- phase products to complete the multi-phase vr solution with minimal external components. it can be configured for 1 ~ 6 phase operation. the mp2953b provides on-chip eeprom to store and restore device configurations. device configurations and fault parameters are easy to program or monitor using the pmbus interface. the mp2953b monitors and reports the output current through cs output from intelli-phase products. the mp2953b is based on a unique digital multi-phase, non-linear control to provide fast transient response to load transient with minimal output capacitors. with only one power loop control method for both steady state and load transient, the power loop compensation is easily configured. features ? 6-phase digital pwm controller ? intel?s vr12.5 compliant ? pmbus compliant ? serial vid interface for programming and monitoring ? pin programmable svid registers ? built-in eeprom to store custom configurations ? automatic loop compensation ? less external components than conventional analog controllers ? phase-shedding at light load to provide high efficiency ? phase-to-phase active current balancing ? input and output voltage, current, and power monitoring ? regulator temperature monitoring ? open-drain fault# signal for fault notification ? rvp/ovp/uvp/ocp/otp/uvlo protection with options of no action, latch, retry, or hiccup ? adjustable load-line regulation ? rohs compliant 5mmx5mm qfn-40 applications ? server core voltage ? graphic card core regulators ? telecom and networking systems ? base stations all mps parts are lead-free, halogen-free, and adhere to the rohs directive. for mps green status, please visit the mps website under quality assurance. ?mps? and ?the future of analog ic technology? are registered trademarks of monolithic power systems, inc.
mp2953b ? digital pwm controller with pmbus for vr12.5 mp2953b rev. 1.01 www.monolithicpower.com 2 10/9/2015 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2015 mps. all rights reserved. typical application mp2953b 6- phase vr12.5 digital controller agnd dgnd vinsen sclk sdio alert# vtt = 1.05v sclk sdio alt# vrrdy vrhot# vrrdy prochot# en en alt_p# pmbus kit scl_p sda_p cpu vdd50 vddhc18 vrflt# +5v pwm6 pwm5 pwm4 pwm3 pwm2 pwm1 vortn vosen fb vdiff cs_sum cs1 cs2 cs3 cs4 cs5 cs6 ccm temp vout pgnd load vin=12v vfs imon iref vdd33 sw pgnd bst vdd agnd en pwm cs temp sync intelli- phase vin sw pgnd bst vdd agnd en pwm cs temp sync intelli- phase vin sw pgnd bst vdd agnd en pwm cs temp sync intelli- phase vin sw pgnd bst vdd agnd en pwm cs temp sync intelli- phase vin sw pgnd bst vdd agnd en pwm cs temp sync intelli- phase vin sw pgnd bst vdd agnd en pwm cs temp sync intelli- phase vin vdd33 addr_p addr_s vboot vdd33
mp2953b ? digital pwm controller with pmbus for vr12.5 mp2953b rev. 1.01 www.monolithicpower.com 3 10/9/2015 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2015 mps. all rights reserved. ordering information part number (*) package top marking mp2953bgu-xxxx (**) qfn-40 (5mmx5mm) see below * for tape & reel, add suffix (e.g. mp2953bgu-xxxx (**) -z). **: ?xxxx? is the configuration code i dentifier for the register settings stored in the eepr om. for the default case, the number will be ?0000.? each ?x? could have a hexadeci mal value between 0 & f. please work with the mps fae to create this unique number even if ordering the ?0000? code. top marking mps: mps prefix yy: year code ww: week code mp2953b: part number lllllll: lot number package reference cs6 en vdd33 pwm1 pwm2 pwm3 pwm4 pwm5 pwm6 ccm scl_p sda_p alt_p# dgnd vrrdy vrhot# vrflt# alt# sdio sclk vboot imon temp vfs vinsen addr_p addr_s iref vdd18 vdd50 cs5 cs4 cs3 cs2 cs1 vdiff vfb vosen vortn cs_sum 1 2 3 4 5 6 7 8 9 10 30 29 28 27 26 25 24 23 22 21 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 agnd
mp2953b ? digital pwm controller with pmbus for vr12.5 mp2953b rev. 1.01 www.monolithicpower.com 4 10/9/2015 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2015 mps. all rights reserved. absolute maxi mum ratings (1) vdd50.......................................?0.3v to +6.5 v vdd18.......................................?0.3v to +2.0 v cs1 to cs6, pwm1 to pwm6, fb, vdiff, vosen, vortn, scl_p, sda_p, alt_p#, ccm, en, vdd33......................?0.3v to +3.6 v all other pins.............................?0.3v to +1.8 v continuous power dissipation (t a = +25c) (2) ???????????????..?? ..3.4 w junction temperature...............................150 o c lead temperature ....................................260 o c storage temperature.............. ?65 o c to +150 o c recommended operating conditions (3) vdd50......................................................... +5v operating junction temp. (t j ). -10c to +125c thermal resistance (4) ja jc qfn-40 (5mmx5mm).............. 36 ....... 5.... q c/w notes: 1) exceeding these ratings may damage the device. 2) the maximum allowable power dissipation is a function of the maximum junction temperature t j (max), the junction-to- ambient thermal resistance ja , and the ambient temperature t a . the maximum allowable continuous power dissipation at any ambient temperature is calculated by p d (max) = (t j (max)-t a )/ ja . exceeding the maximum allowable powe r dissipation produces an excessive die temperature, causing the regulator to go into thermal shutdown. internal thermal shutdown circuitry protects the device from permanent damage. 3) the device is not guaranteed to function outside of its operating conditions. 4) measured on jesd51-7, 6-layer pcb.
mp2953b ? digital pwm controller with pmbus for vr12.5 mp2953b rev. 1.01 www.monolithicpower.com 5 10/9/2015 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2015 mps. all rights reserved. electrical ch aracteristics vdd50 = 5 v, en = 1v, vid = 0.50 v to 2.6 v, current going into pin is positive, t j =-10c to 125c, unless otherwise noted. parameter symbol condition min typ max units remote sense amplifier bandwidth (5) gbw (rsa) 20 mhz vortn current i rtn -70 -400 a vosen current i vosen 70 400 a oscillator frequency f osc iref=1.23v; riref=61.9k ? 1.56 mhz system interface control inputs en input low voltage vil (en) 0.4 v input high voltage vih (en) 0.8 v enable high leakage iih (en) en=2v 3.6 a enable delay t a en high to svid ready 2 5 ms thermal throttling control vrhot# low output impedance i vrhot# = 20ma, t a = 25c 8 12 ? vrhot# high leakage current vrhot = 1.8v -3 3 a imon output current gain accuracy i mon /i cs_sum measured from i cs_sum to i mon, i cs_sum =1.2ma 1:32 a/a comparator (vfb & vref) propagation delay (5) t pd 10 ns common-mode range 0 2.6 v comparator (vfb & vref-20mv) propagation delay (5) t pd 10 ns common-mode range 0 2.6 v comparator (protection) under-voltage threshold v diff (uv) relative to reference dac voltage ? 300 mv relative to reference dac voltage 300 mv over-voltage threshold v diff (ov) relative to protection dac voltage 400 mv
mp2953b ? digital pwm controller with pmbus for vr12.5 mp2953b rev. 1.01 www.monolithicpower.com 6 10/9/2015 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2015 mps. all rights reserved. electrical characteristics (continued) vdd50 = 5 v, en = 1v, vid = 0.50 v to 2.6 v, current going into pin is positive, t j =-10c to 125c, unless otherwise noted. parameter symbol condition min typ max units relative to rtn, vdiff is falling 0 mv reverse voltage detection threshold (5) v osen (rv) relative to rtn, vdiff is rising 30 mv ccm output output low voltage v ol i ccm(sink) = 400 a 10 500 mv output high voltage v oh i ccm(source) = -400 a 3 vdd33- 0.02 v pwm outputs output low voltage v ol (pwm) i pwm(sink) = 400 a 10 200 mv output high voltage v oh (pwm) i pwm(source) = -400 a 3.15 vdd33- 0.02 v rise and fall time (5) c = 10pf 10 ns pwm tri-state leakage pwm = 1.5v; en = 0v -1 1 a supply supply voltage range vdd50 4.5 5 5.5 v supply current i vdd50 en=high. both the svid bus and the internal id bus are idle. no-load condition. 6-phase configuration. 16 ma uvlo threshold voltage vdd uvlo vdd50 is rising 4.13 4.5 v uvlo hysteresis (5) vdd uvlo vdd50 is falling 180 mv 1.8v regulator 1.8v regulator output voltage vdd18 i vdd18 = 0ma 1.8 v 1.8v regulator load capability i vdd18 vol = vdd18 - 40mv 30 ma 3.3v regulator 3.3v regulator ouput voltage vdd33 i vdd33 = 0ma 3.3 v 3.3v regulator load capability i vdd33 vol = vdd33 - 40mv 30 ma
mp2953b ? digital pwm controller with pmbus for vr12.5 mp2953b rev. 1.01 www.monolithicpower.com 7 10/9/2015 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2015 mps. all rights reserved. electrical characteristics (continued) vdd50 = 5 v, en = 1v, vid = 0.50 v to 2.6 v, current going into pin is positive, t j =-10c to 125c, unless otherwise noted. parameter symbol condition min typ max units svid interface (5) v il logic low 0.45 v v ih logic high 0.65 v cpu interface voltage (sdio, sclk) v hyst hysteresis 50 mv termination resistance (sdio, sclk, alt#) (5) r pu 50 55 tbd ? leakage current (sdio, sclk, alt#) il 0v to vtt -10 10 a pad capacitance (sdio, sclk, alt#) c pad 4 pf pin capacitance (sdio, sclk, alt#) (5) c pin 5 pf buffer on resistance (sdio, sclk, alt#) (5) r on 4 5 ? maximum voltage (sdio, sclk, alt#) v max transient voltage including ringing -0.3 2.1 v slew rate (sdio, sclk, alt#) (5) 2nh, 4pf load 0.5 2 v/ns vr clock to data delay (5) 4 8.3 ns setup time 7 ns hold time 14 ns dac (reference voltage) range 2.88 v resolution per lsb 10 mv output voltage slew rate (5) 100 mv/ s dac (vout calibration) range 350 mv resolution 8 bit dac (protection) range adjustable via the pmbus 0.97~3.54 v resolution 10 mv
mp2953b ? digital pwm controller with pmbus for vr12.5 mp2953b rev. 1.01 www.monolithicpower.com 8 10/9/2015 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2015 mps. all rights reserved. electrical characteristics (continued) vdd50 = 5 v, en = 1v, vid = 0.50 v to 2.6 v, current going into pin is positive, t j =-10c to 125c, unless otherwise noted. parameter symbol condition min typ max units power management features vin uvlo turn-on threshold adjustable via the pmbus 10.2 v vin uvlo turn-off threshold adjustable via the pmbus 9 v thermal protection threshold dbh = 961eh 150 o c thermal protection hysteresis dbh = 961eh 30 o c pmbus dc characteristics (alt_p, sda_p, scl_p) input high voltage v ih scl_p, sda_p 2.4 v input low voltage v il scl_p, sda_p 0.8 v input leakage current scl_p, sda_p, alt_p -10 10 a output low voltage v ol alt_p sinks 2ma 400 mv maximum voltage v max transient voltage including ringing -0.3 3.3 3.6 v pin capacitance (5) c pin 10 pf pmbus timing characteristics (5) o perating frequency range 10 400 khz bus free time period between stop and start condition 4.7 s holding time 4.0 s repeated start condition setup time 4.7 s stop condition setup time 4.0 s data hold time 300 ns data setup time 250 ns clock low time out 25 35 ms clock low period 4.7 s clock high period 4.0 50 s clock/data fall time 300 s clock/data rise time 1000 s notes: 5) guaranteed by design or characterization data, not tested in production.
mp2953b ? digital pwm controller with pmbus for vr12.5 mp2953b rev. 1.01 www.monolithicpower.com 9 10/9/2015 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2015 mps. all rights reserved. typical performanc e characteristics
mp2953b ? digital pwm controller with pmbus for vr12.5 mp2953b rev. 1.01 www.monolithicpower.com 10 10/9/2015 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2015 mps. all rights reserved. typical performanc e characteristics (continued) v out 500mv/div. v cs1 600mv/div. v pwm1 3v/div. v pwm2 3v/div. v out 700mv/div. v temp 300mv/div. v cs 1v/div. v pwm 2v/div.
mp2953b ? digital pwm controller with pmbus for vr12.5 mp2953b rev. 1.01 www.monolithicpower.com 11 10/9/2015 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2015 mps. all rights reserved. pin functions pin # name i/o description 1 cs5 i phase 5 current sense input. float cs of the unused phase. 2 cs4 i phase 4 current sense input . float cs of the unused phase. 3 cs3 i phase 3 current sense input. float cs of the unused phase. 4 cs2 i phase 2 current sense input. float cs of the unused phase. 5 cs1 i phase 1 current sense input. 6 vdiff o differential remote sense amplifier output. 7 fb i/o feedback. fb sources a current proportion al to the sensed output current (idroop). this current flows through t he resistor between fb and vdiff to create a voltage drop proportional to the load current. ensure the resistor between vdiff and fb has a value that will set a proper load line. 8 vosen i positive remote voltage sense input. vosen is connected directly to the vr output voltage at the load and should be routed differentially with vortn. 9 vortn i remote voltage sensing return input. vortn is connected directly to ground at the load and should be routed differentially with vosen. 10 cs_sum i total phase current, which monitors avp. connect the active phase cs signal to cs_sum through current-sense resistors. 11 vboot i/o boot voltage setting . 12 imon i/o analog total load current signal. imon sources a current proportional to the sensed total load current from cs_sum. connect an external resistor from imon to gnd to program the gain. 13 temp i analog signal from the vr to the vid controller to indicate the power stage temperature. the mp2953b only supports temperature sensing from intelli-phase. connect all of intelli-phase?s vtemp pins together to produce the maximum junction temperature and then connect to temp. 14 vfs i/o switching frequency setting. 15 vinsen i input voltage sensing . connect vinsen to the system input voltage through a resistor divider. 16 addr_p i/o pmbus address setting. 17 addr_s i/o svid address setting. 18 iref i internal bias current. connect an 61.9k ? resistor from iref to gnd. 19 vdd18 o 1.8v ldo output for current sense. connect a 1f bypass capacitor to digital ground. 20 vdd50 i 5v analog power supply. connect a 10f bypass capacitor to digital ground. 21 sclk i source synchronous clock from the cpu . frequency range from 10mhz to 26mhz. 22 sdio i/o data signal between the cpu and vid controller. 23 alt# o alert . alt# is an open-drain output. it is the alert signal from the vid controller to the cpu.
mp2953b ? digital pwm controller with pmbus for vr12.5 mp2953b rev. 1.01 www.monolithicpower.com 12 10/9/2015 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2015 mps. all rights reserved. pin functions pin # name i/o description 24 vrflt# o vr fault. vrflt# is an open-drain output. when vin or vout ovp occurs, vrflt# is asserted to shut down the input power supply. 25 vrhot# o voltage regulator thermal throttling logic output. vrhot# is an open- drain output. vrhot# pulls low actively if the monitored temperature exceeds the programmed vrhot# te mperature threshold. 26 vrrdy o vr ready output. vrrdy is an open-drain output that signals when the output voltage is outside of the proper operating range. a vtt rail is expected for pull up; however, some systems may pull up to a maximum voltage of 3.3v with an external pull-up circuit. 27 dgnd i/o digital ground. 28 alt_p# o open-drain output that asserts low when a warning has occurred. 29 sda_p i/o data signal between the pmbus controller and the vid controller. 30 scl_p i source synchronous clock from the pmbus controller. 31 ccm o forced ccm operations enable. ccm stays high in power state 0 and 1. it pulls low actively during ps2/3 to enable dcm operation. 32 pwm6 o 33 pwm5 o 34 pwm4 o 35 pwm3 o 36 pwm2 o 37 pwm1 o tri-state logic-level pwm outputs . each output is connected to the input of intelli-phase?s pwm pin. the logic levels are 0v for low logic and 3.3v for high logic. the output is set to tri-state (high-z) to shut down both the high-side mosfet and the low-side mosfet of intelli-phase. 38 vdd33 o 3.3v ldo output for the internal digital power supply. connect a 1f bypass capacitor to digital ground. 39 en i enable control for the controller. 40 cs6 i phase 6 current sense inputs. float cs of the unused phase. pad agnd i/o analog ground.
mp2953b ? digital pwm controller with pmbus for vr12.5 mp2953b rev. 1.01 www.monolithicpower.com 13 10/9/2015 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2015 mps. all rights reserved. operation the mp2953b is a digital multi-phase vr12.5 compliant controller for intel microprocessors. it operates in 1-, 2-, 3-, 4-, 5-, or 6-phase. it contains blocks of precision dac and adc, differential remote voltage sense amplifier, fast comparators, current sense amplifiers, internal loop compensation, load-line setting, vr_ready monitor, temperature monitor, pmbus interface, svid interface, and eeprom for custom configuration. fault protection features include under-voltage lockout (vin-uvlo), over-current protection (ocp), over-voltage protection (ovp), under- voltage protection (uvp), over-temperature protection (otp), and reverse-voltage protection (rvp). pwm generator & phase interleaving & power state protection & fault monitor sensing & monitor current balancing & vout dc calibration x1 fb temp vinsen pmbus interface & register memory (eeprom) vortn vosen cs3 cs1 cs2 cs4 mux adc vdiff cs5 cs6 svid interface & register reference generator & internal loop compensation power vcc & oscillator pwm3 pwm4 pwm5 pwm6 ccm pwm1 pwm2 vdd18 vdd33 en vdd50 agnd dgnd i droop dac dac vid vosen ov1 ov2 uv rv 30mv vdiff ocp_lim cs1 oc1 oc2 oc3 oc6 oc4 oc5 cs2 cs4 cs5 cs6 cs3 cm cm cm cm cm cm cm dac dac ovp_lim vid+300mv cm cm cm vid-300mv sda_p scl_p alt_p# iref cs_sum imon addr_s addr_p vboot vfs vrflt# sclk sdio alt# vrrdy vrhot# vr_settle cm vid-20mv v fb v fb v dc_trim dac v ac_trim 1.23v i droop 1:8 1:32 - adc figure 1. system functional block
mp2953b ? digital pwm controller with pmbus for vr12.5 mp2953b rev. 1.01 www.monolithicpower.com 14 10/9/2015 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2015 mps. all rights reserved. eeprom operation the mp2953b provides eeprom for storing application configuration parameters. the default values are pre-programmed at the factory. the data can be programmed again using store_user_all command via the pmbus. eeprom is read automatically during the power- on sequence or by receiving the restore_user_all command from the pmbus. the state machine of the mp2953b is shown in fig. 2. eeprom operation is accomplished easily with mps gui software. eeprom is subject to more than 100,000 erase/write cycles. protect = 1 protect = 1 stdy copy eeprom system initial power active wait 1 wait 2 eeprom faults por data invalid data is ok waiting fault clear protect = 1 protect = 0 command off command on shut down command off command off soft start figure 2. system state machine system configuration the mp2953b provides a differential output voltage sense, an input voltage sense, and an output enable function. working with the intelli- phase (mps driver mos), the mp2953b senses the per-phase current and the maximum temperature among the power mosfets with minimal external components. the pwm of the mp2953b outputs 3.3v compatible tri-state signals before outputting power to the load. the boot voltage, per-phase switching frequency, svid address, and pmbus slave address can be set using pin configurations or using the registers via the pmbus. the mp2953b can be configured as a 3~6 phase operation application via the pmbus (see table 1). table 1. phase configuration and active pwm pins mfr_vr_config [14:12] phase number active pwm pins 3?b100 2 1, 3 3?b011 3 1, 2, 3 3?b100 4 1, 2, 3, 4 3?b101 5 1, 2, 3, 4, 5 3?b110 6 1, 2, 3, 4, 5, 6 an unused pwm enters tri-state, and the active phase becomes interleaving automatically. power-on configuration the mp2953b is supplied by +5v voltage, its internal ldos produce +3.3v voltage for the analog circuit and +1.8v voltage for the digital circuit. the system is re-set by the internal power-on re-set signal (por). after the system exits por, the data in the eeprom loads to the registers to configure the vr operation. if the setting is loaded from pins, then resistors with 1% tolerance must be connected from vboot, vfs, addr_s, and addr_p to ground in order to set the parameters of the controller. the initialization process takes 700 s.
mp2953b ? digital pwm controller with pmbus for vr12.5 mp2953b rev. 1.01 www.monolithicpower.com 15 10/9/2015 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2015 mps. all rights reserved. eeprom fault and wait state if the data in the eeprom is invalid, the system enters the eeprom fault state and waits for the error to clear. the data in the eeprom is ignored if the system detects an eeprom fault. the following 3 actions clear the eeprom fault in order to re-set with the default value in the register: 1. clear the eerpom fautl via the pmbus; 2. store the register data into the eeprom via the pmbus and re-start again; 3. receive the setvid command and run the vr with default values in the registers. once the registers are loaded from the eeprom, the mp2953b enters a soft-start state. if any of the conditions below occur, the system will remain in the waiting state until the conditions are removed: 1. protection is triggered (i.e. the sense input voltage is under the vin_on threshold), or the sensed temperature is above the otp_limi, ovp1. the system enters the wait2 state until the protection signal is re- set. 2. the internal enable command is off, the system enters the wait1 state until the enable command is on; the eeprom will be read again. soft-start (ss) before entering the power-active state, the mp2953b executes the soft-start process to charge the output capacitor with the setvid_slow slew rate (until the reference reaches the boot voltage). fig. 3 shows the soft-start process with a pre- bias function. the ccm signal is low to turn off all phases until the reference voltage rises above the output voltage. once the pre-bias is over, the controller sets pwm1 high (with a narrow minimum on pulse). the controller increases the on-time according to the vid and sensed input voltage. in next cycle, the controller triggers phase 2 to turn on and exit tri-state. all other phases will exit tri-state in this manner. figure 3. soft-start with pre-bias if boot voltage is nonzero, the output voltage ramps up to the boot voltage and asserts alert#. alert# de-asserts after the status1 register is read. when receiving a new setvid command, the controller ramps to the target voltage with the rate of svid_fast or svid_slow. if the boot voltage or the icc max is set initially to 0, the pwm is kept in tri-state until a valid svid voltage is received, and the icc max is set above 0. the controller then ramps the voltage to the target value and asserts alert#. after the controller completes the soft-start process, it is ready to output power to the load and assert vr_ready. power active the mp2953b applies a digital, non-linear control to provide fast transient response and easy loop compensation. the duty cycle of each phase?s pwm updates in real-time, according to the input voltage and reference voltage. figure 4(a) shows the steady-state performance with load current at 160a.
mp2953b ? digital pwm controller with pmbus for vr12.5 mp2953b rev. 1.01 www.monolithicpower.com 16 10/9/2015 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2015 mps. all rights reserved. figure 4(a). steady state with load @160a load transient performance is illustrated in figures 4(b)?(d). the mp2953b adaptively changes the switching frequency of each individual phase during load transient to achieve fast closed-loop speed. only one set of loop compensation is needed, so it is very easy to set the loop parameter. fig. 4(b) shows no ring-back when the load steps up from 36a to 180a. fig. 4(c) shows that the overshoot of the output voltage is small during load release. fig. 4(d) shows the high-load transient rate; the output voltage is stable. the mp2953b meets intel vr12.5 standards with a minimum number of output capacitors. figure 4(b). load step up @ 1khz figure 4(c). load step down @ 1khz figure 4(d). load step @1mhz power state change the svid bus changes the vr into different power states to achieve high efficiency during light-load conditions. these states are entered by programming the power-state register using svid?s setps command. the vr optimizes its power loss to flatten the efficiency curve over the operating current range with the power-state commands issued by the cpu. in ps0 mode, all phases run in ccm. in ps1 mode (<20a load, typically), only one phase runs with synchronous switching; the other phases are in tri-state. in ps2 mode (<5a load, typically), only one phase runs in the diode emulation mode; the switching frequency decreases automatically due to the light-load condition.
mp2953b ? digital pwm controller with pmbus for vr12.5 mp2953b rev. 1.01 www.monolithicpower.com 17 10/9/2015 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2015 mps. all rights reserved. during the dynamic vid transition issued by the svid commands of either setvid_fast or setvid_slow, the power state is changed to ps0 by default and runs in full-phase pwm mode. once the output is well regulated to the new target voltage, the power state stays in ps0 until the cpu sends a new command to change the power state. the mp2953b implements the psi function in the following ways: 1) tri-state of pwm: when the vr receives the setps1 command, it sets pwm2~6 outputs to tri- state (high-z) or the third level; 2) ccm control: when the vr receives the setps2 command, phase 1 must enter dcm. the vr will set pwm2~6 outputs to tri-state and pull ccm low (which is connected to sync of intelli-phase). then phase 1 will enter diode emulation mode. figures 5(a) and 5(b) show the phase-shedding and phase-adding process when the vr receives the setps command. three sets of registers are provided to set the loop compensation of the power state. customers can use the mps gui to set these registers automatically. customers only need to select the fast transient performance loop or the steady-state performance loop. figure 5(a). 1-phase ccm ? 6-phase ? 1-phase ccm figure 5(b). 1-phase dcm ? 6-phase ? 1-phase dcm shutdown the mp2953b enters shutdown mode in the following ways: 1. when en pulls low, the vr begins high-z shutdown. 2. when the operation command is set to soft off, the vr will soft shut down with the rate of svid_slow. 3. when the operation command is set to immediate off, all pwm signals will enter tri- state to turn off all phases. 4. uvp, vin_uvlo, ocp, and otp turn off all phases immediately by forcing all pwm signals to enter tri-state. 5. ovp1/2 forces all pwm signals low to turn off all high-side mosfets and turn on all low- side mosfets to discharge the voltage in the output capacitor. if the vr is shut off by the enable signal, it enters the wait1 state after shutdown. the vr can be re-started by setting the enable signal to high. when enable is high, the system will read eeprom again. if the vr is shut off by the protection signal, it enters the wait2 state after shutdown. the vr can be re-started by re-setting the protection signals. once the protection signals are re-set, it takes 12.5ms before the soft-start begins. this state occurs when the protection mode is set to hiccup mode or retry mode.
mp2953b ? digital pwm controller with pmbus for vr12.5 mp2953b rev. 1.01 www.monolithicpower.com 18 10/9/2015 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2015 mps. all rights reserved. if the vr is in the wait2 state and the enable signal is pulled low, the vr enters the wait1 state to wait for the system to re-start. this state occurs if the protection mode is set to latch mode or retry mode. output voltage sense the output voltage is remote sensed with the differential amplifier. the sensed output voltage is used for loop compensation, over-voltage protection, under-voltage protection, and monitoring via the pmbus. the output voltage with the load-line regulation component is compared with the reference voltage from the vid-dac. the error is converted to a series of high-speed digital signals by the special adc. the factory trimmed bandgap voltage reference and differential remote sense amplifier ensures precise setpoint and output voltage accuracy. input voltage sense the 12v supply voltage on vinsen is sampled and used for vin_uvlo, vin_ovp fault protection, and monitoring via the pmbus. a 16:1 attenuation network is connected to vinsen (see fig. 6). recommended values for a 12v system are r vin_1 = 15k ? and r vin_2 = 1k ? , with a 1% tolerance or better. usually, c vinsen is not required or may be populated up to a maximum of 10nf for noise suppression. figure 6. vin resistor divider network total current sense the total current is sensed from cs_sum; a proportional current comes from imon. place a resistor from imon to ground to generate a voltage proportional to the output current. the imon voltage is sampled and converted by adc and then converted to the direct format or iccmax format for the current report. the r imon is calculated with equation (1). 5120 imon ccmax r k i d : (1) where 1 by default (which can be used to increase the current report resolution). the current report for the cpu is used to avoid exceeding the thermal design point and maximum current capability of the system. also, the current report is used for total current fault protection. the mp2953b contains a user-programmable scaling factor and a programmable current offset. the programmable parameters allow users to match the imon scaling to the design?s voltage regulator tolerance band (vrtob) calculation. this provides the most accurate current reporting across the entire load range and maximizes the performance of intel turbo. inductor current sense the mp2953b works with mps intelli-phase to sense the phase inductor current and the total current (see fig. 7). the cycle-by-cycle current information is used for phase-current balancing, over-current protection, and active voltage positioning (output-voltage droop). the current sense gain is 10 a/a for intelli- phase products. the resistor r cs is connected from cs to cs_sum. cs_sum is a 1.23v constant voltage, and it is capable of sinking small current to provide voltage shifts that meet the operating voltage range of cs. different intelli-phase products have different operating voltage ranges of cs, v cs_min , and v cs_max . refer to each intelli-phase?s datasheet to determine the minimum and maximum operating voltage range. use equation (2) to determine a proper r cs value: cs _ min cs cs cs _ max 6 cs l vir1.23vv i i 10 10 uu (2) paired with intelli-phase, the mp2953b does not need temperature compensation
mp2953b ? digital pwm controller with pmbus for vr12.5 mp2953b rev. 1.01 www.monolithicpower.com 19 10/9/2015 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2015 mps. all rights reserved. and impendence matching to achieve accurate current sense. intelli -phase vin sw pgnd bst vdd agnd cs mosfe t driver +5v r cs mp2953 cs_sum cs1 cs2 cs3 cs4 cs5 cs6 figure 7. current sense with intelli-phase temperature sense the mp2953b measures the external temperature by connecting all the intelli-phase vtemp (see fig. 8). the sensed temperature is used for over-temperature fault protection, and the assert vrhot# signal is used for the cpu. intelli -phase vin sw pgnd bst vdd agnd vtemp mosfe t driver +5v intelli -phase vin sw pgnd bst vdd agnd vtemp mosfe t driver +5v mp2953 temp figure 8. external temperature sense vtemp of intelli-phase is a voltage output proportional to the junction temperature. the junction temperature can be calculated from equation (3): temp junction o o junction v 100mv t 10mv / c for t 10 c + = > (3) for example, if the vtemp voltage is 700mv, the junction temperature of that intelli-phase is 80 . vtemp can not go below 0v, so it will read 0v for junction temperature lower than 10 . dynamic voltage identification (dvid) the mp2953b supports dynamic vid change through three svid commands: setvid_fast, setvid_slow, and setvid_decay. by default, the slew rate for setvid_fast is 20mv/ s; the slew rate for setvid_slow is 5mv/ s; the slew rate for setvid_decay is determined by the load current and output capacitor bank. if the vr receives a setvid_fast/slow command in a low-power state (ps1/2/3), the vr will enter ps0 then change voltage, so it will always operate in full-phase pwm mode during a voltage change by setvid_fast/slow. during dynamic vid, ovp2 (which is vid +300mv) is temporarily disabled. however, ovp1 (which is vout_max +400mv) remains enabled. the mp2953b applies an advanced digital control method to improve the output voltage performance during setvid_fast/slow voltage changes. ramping up when the output voltage is ramping up, the inductor current becomes higher to charge the output capacitors. this current introduces a large positive droop voltage and lowers the output voltage. once ramping ends, the output voltage may be smaller than the minimum regulation tolerance budget (5s after alert#), which is unacceptable. ramping down when the output voltage is ramping down, the inductor current becomes smaller to discharge the output capacitors (which will continue to discharge the output capacitors when ramping ends and may lead to an output-voltage undershoot. the mp2953b applies a low-pass filter for the vid-dac to smooth out the reference voltage when the output voltage is ramping down.
mp2953b ? digital pwm controller with pmbus for vr12.5 mp2953b rev. 1.01 www.monolithicpower.com 20 10/9/2015 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2015 mps. all rights reserved. fig. 9 shows the output voltage of setvid_fast upward following the completion of the previous setvid_fast downward (sr = 20mv/ s). figure 9. setvid_fast downward ? setvid_fast upward if the controller receives a setps command while the output voltage is ramping from the previous setvid command (except for the setvid_decay command), then the controller will send a reject response (see fig. 11(b)) to the setps command as an indication that it cannot carry out the command. figures 10(a) and 10(b) show different categories of decay preemption. the dynamic vid process is very smooth as there is no undershoot or ringback of the output voltage during the transient. figure 10(a). decay (interrupted) ? setvid_fast (interrupted) ? setvid_fast (finished) figure 10(b). setvid_fast (interrupted) ? decay (interrupted) ? setvid_fast (finished) ? setvid_fast (finished) pmbus & svid communication the mp2953b supports real-time monitoring for the vr operation parameters and status with the pmbus and svid interface. table 2 lists the monitored parameters. table 2. pmbus & svid monitored parameters parameter pmbus svid output voltage x x output current x x output power x x temperature x x input voltage x x phase1~6 current x powergood x x ov x oc x x uv x ot x x cml x fault monitoring and protection features the mp2953b supports fault monitoring and the following protection features: z vin uvlo : a) the vr shuts off immediately if the input voltage is below vin_off, and it re- starts when the input voltage is above vin_on.
mp2953b ? digital pwm controller with pmbus for vr12.5 mp2953b rev. 1.01 www.monolithicpower.com 21 10/9/2015 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2015 mps. all rights reserved. b) the vr latches if the input voltage is above vin_ov_fault_limit. c) the vr is warned if the input voltage is below vin_uv_warning_limit. z under voltage : when the output voltage is below vid ? 300mv for a pre-set time, the vr either latches off or re-starts depending on the user selection via the pmbus. z over voltage : a) when the output voltage is above vid + 300mv for a pre-set time, the vr latches off (with all the low-side mosfets turned on). it can be programmed to re- start after the fault condition clears. b) when the output voltage is above vout_max + 400mv for another pre-set time, the vr latches off (with all the low- side mosfets turned on). z reverse voltage : all the low-side mosfets turn off if the output voltage is below 30mv. z over current : when the total current is above the ocp level for a pre-set time, the vr latches off or re-starts. z over-temperature indicator (vrhot#, active low) : when the temperature is above otp_limit, the vr latches until the temperature falls below otp_limit- otp_hys. z fault# signal (cfp) : when vin is above vin_ov_fault_limit or the output voltage is above vout_max +400mv, then fault# pulls low actively. z cml : the pmbus communication fault. z eeprom fault : the data in the eeprom is invalid. all fault conditions can be monitored via the pmbus. ovp, ocp, and uvp modes have options of no action, latch, retry, or hiccup mode. after the fault condition clears, the mp2953b waits12.5ms before attempting to re-start again. a 12.5ms delay ensures a sufficiently low duty-cycle stress rate to prevent regulator components from being damaged by power cycling. for latched protection mode, external intervention is required to clear the latch before the vr can re-start again. external intervention includes the enable signal toggle, controller power-supply recycle, or input-voltage supply toggle. the fault status is record in the registers. once triggered, the fault registers report faults even if the fault condition no longer exists. fault registers may be cleared manually by issuing a fault clear command, controller power-supply cycle, or the enable signal toggle (either by en or command enable toggle). the following is a brief description of each fault: over-voltage protection (ovp) the ovp circuit monitors the output voltage for an over-voltage condition. the over-voltage signal generation is shown in fig. 11. vid 300mv comp vdiff ov2 comp ov1 comp uv comp rv 30mv vosen dac vout_max+400mv figure 11. ov, uv, and rv signal generation there are two levels of over-voltage protection: 1. ovp2 (vid+300mv) and 2. ovp1 (vout_max + 400mv). the ovp2 signal is blanked during the soft-start and soft-shut down process to avoid a false trigger by a pre-bias condition. also, the ovp2 monitor is disabled during a vid decay transition. it re-activates after finishing the vr settle re- assertion transition.
mp2953b ? digital pwm controller with pmbus for vr12.5 mp2953b rev. 1.01 www.monolithicpower.com 22 10/9/2015 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2015 mps. all rights reserved. fig. 12 summarizes the blanking conditions for ovp2 monitor. the ovp1 monitor is active when the controller is enabled, regardless of fault conditions. this ensures that the load is protected against high-side mosfet leakage while the mosfets are turned off. in the event of an ovp condition, the pwms are latched low with ccm=1. this turns off the high-side mosfets and turns on the low-side mosfets to crowbar the output voltage. the ovp latch can be re-set only by the enable toggle, the vcc toggle, or reverse-voltage protection (rvp). fig. 13 shows the ovp fault latch for both levels. svid bus vid vout vrrdy vid+300mv vid during start-up, ovp2 is blanked until the soft-start is over ovp2 is blanked for 100us during the setvid_fast/setvid_slow vid transient vid+300mv ovp2 is blanked during the setvid_decay vid transient ovp_da_limit en pwm1 vr settle 100us soft-start setvid_fast/ setvid_slow setvid_decay pwm2~6 ccm vboot getreg status packet setvid fast pay load a c k 1 a c k 0 pay load a c k 1 a c k 0 getreg status packet setvid decay pay load a c k 1 a c k 0 pay load a c k 1 a c k 0 getreg status packet pay load a c k 1 a c k 0 figure 12. ovp protection blanking conditions
mp2953b ? digital pwm controller with pmbus for vr12.5 mp2953b rev. 1.01 www.monolithicpower.com 23 10/9/2015 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2015 mps. all rights reserved. ovp1 is always active hs off and ls on hs off and ls off,tri-state ovp2 vid+300mv rvp vid+300mv retry recycle en ovp1 rvp ovp_da_limit getreg status packet pay load a c k 1 a c k 0 vboot getreg status packet pay load a c k 1 a c k 0 vboot note:in case the hs breaks down, vo will ramp to ovp again hs off and ls on 0mv vr ready vout vid svid bus pwm ccm reset en mfr_ovp_set_delaytime 0.1us figure 13. ovp and rvp fault protection
mp2953b ? digital pwm controller with pmbus for vr12.5 mp2953b rev. 1.01 www.monolithicpower.com 24 10/9/2015 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2015 mps. all rights reserved. over-current protection (ocp) the mp2953b utilizes the valley point over- current limit method to limit each phase current. if the present phase current is higher than the setting valley point, then this phase will not turn on until its current falls below the setting level. if the present phase is blocked for 150ns, then the next phase will turn on instead so as to regulate the output voltage at the set point. the valley point over-current level can be programmed via the pmbus to limit the per- phase current. the total current protection is triggered if the sensed average total current is higher than the oc threshold. since this protection averages the output current over many switching cycles, the average current ocp threshold can be set very close to the expected maximum output load for accurate over-current protection. fig. 14 shows the ocp process for total current protection. the total current protection is disabled during the soft-start process, and it is enabled when soft start has finished. vout ccm pwm vrrdy oc ocp iphase phase_ocp_lim iout 500 us total_ocp_lim figure 14. oc protection for total current fig. 15 shows the process when the output is shorted to ground. during this process, per- phase ocp limits the phase current. after a pre-set time, the vr is shut off by the total current ocp. figure 15. ocp with output dead short under-voltage protection (uvp) if the output voltage is below vid ? 300mv for a given time, the system triggers uvp and immediately shuts down by turning off all phases. fig. 16 shows the uvp process. normally, uvp is triggered when pwm signals are blocked by the oc signals (when the per- phase current limit is reached) as shown in fig. 17. figure 16. under-voltage protection
mp2953b ? digital pwm controller with pmbus for vr12.5 mp2953b rev. 1.01 www.monolithicpower.com 25 10/9/2015 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2015 mps. all rights reserved. figure17. uvp triggered when per-phase current is limited reverse -voltage protection (rvp) a large reverse inductor current may cause negative output voltages, which harm the cpu and other output components. the mp2953b provides rvp without additional system costs. vosen monitors the output voltage (see fig. 10). any time the vosen voltage falls below 30mv, the mp2953b triggers rvp by latching all pwm outputs to high-z state. the reverse inductor current can re-set quickly to 0a by dissipating the energy in the inductor to the input dc voltage source through a forward- biased body diode of the high-side mosfets. occasionally, ovp results in negative output voltage because turning on all low-side mosfets leads to a very large reverse inductor current. the vr controller?s rvp monitoring function remains active even after ovp latch-off to prevent damage to the load by negative voltage. the rvp latch can only be re-set by toggling enable, power cycling vcc, or when ovp occurs (see fig. 13). catastrophic failure protection (cfp) the mp2953b has a dedicated cfp output which triggers in the event of ovp1 or input voltage above vin_ov_fault_limit. in server computer system s, this signal is used commonly to shut down immediately the input supply (by firing a shunting scr in order to blow a fuse or by turning off the ac power supply). this feature is active during the power- on sequence in case a computer shuts down, and the user just recycles the power supply?s ac input. vr_hot# the vr_hot# fault is asserted when the sensed external temperature exceeds the temperature?s maximum threshold. it is used for fault reporting only and it can not shut down the system. also, vr_hot# has a fixed 3c hysteresis and is enabled after the initialization state. vr_hot# is initialized in high-z state upon device power-up. eeprom fault if the data in the eeprom is checked as invalid, the system enters the eeprom fault state and waits for the error to clear. it is reported in the fault register. communication failure a data transmission fault occurs when information is not properly transferred between the devices. several data transmission faults are listed below: ? sending too few data ? reading too few data ? host sends too many bytes ? reading too many bytes ? improperly set read bit in the address byte ? unsupported command code the data transmission faults assert alt_p#. the clear_faults command de-asserts alt_p#; however, if the faults still exist, alt_p# asserts again. active voltage positioning (avp) the mp2953b supports avp by connecting r droop between v fb and v diff . an internal current-sense circuit produces the i droop current source (which is 1/8 of the total current signal) from cs_sum. i droop injects to r droop from vfb to produce the feedback
mp2953b ? digital pwm controller with pmbus for vr12.5 mp2953b rev. 1.01 www.monolithicpower.com 26 10/9/2015 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2015 mps. all rights reserved. voltage with droop voltage for regulation with the reference voltage. given the application?s need for rll load-line regulation, r droop can be calculated according to equation (4): ll droop cs 8r r k = (4) where k cs is the current sense gain of intelli- phase. phase current balancing the per-phase current is sensed and compared with the average phase current. each phase?s pwm on time is adjusted individually to balance the currents. the mp2953b applies - modulation and delay line loop in the current balance modulation so as to increase the resolution of the current balance modulation and greatly reduce the jitter of t on . the resolution of the time modulation of the digital system is 5ns. by applying - modulation, the digital ton resolution can be increased to 0.08ns. figures 18(a) and 18(b) show phase current balance results with and without - modulation. figure 18 (a). phase current balance without - modulation figure 18(b) . phase current balance with - modulation test mode the mp2953b provides test mode for users to test the chip with open-loop operation. in order to avoid the chip being protected, ovp1/2, uvp, otp, ocp, and vin_uvlo should be disabled via the pmbus. svid interface to support multiple vr devices used on the same svid bus, the registers mfr_addr_svid or addr_s are used to program the svid address for each vr. the svid address is a 4-bit code. there are 14 addresses for up to 14 voltage regulator controllers or voltage rails. the final addresses 0eh and 0fh are ?all call? addresses and all the vr controllers respond to these addresses. the ?all call? address is used only with setvid or setps commands. it can not be used with get, setregadr, or setregdat commands. the vr will nak those commands with an ?all call? address. the vr acknowledges an ?all call? address in the same manner as a single address. to get more accuracy value from the pin configuration, place a 1% tolerance resistor (r top ) from the pin to 3.3v and a resistor (r bottom ) from the pin to ground. table 3 shows resistor values for different svid addresses.
mp2953b ? digital pwm controller with pmbus for vr12.5 mp2953b rev. 1.01 www.monolithicpower.com 27 10/9/2015 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2015 mps. all rights reserved. table 3. svid address by addr_s pin svid address r top (k ? ) 1% r bottom (k ? ) 1% 00h ns 0 01h 3.32 0.1 02h 3.32 0.178 03h 3.32 0.301 04h 3.32 0.422 05h 3.32 0.562 06h 3.32 0.698 07h 3.32 0.887 08h 3.32 1.1 09h 2.0 0.806 0ah 2.0 0.931 0bh 2.0 1.07 0ch 2.0 1.27 0dh 2.0 1.65 pmbus interface to support multiple vr devices used with the same pmbus interface, the registers mfr_addr_pmbus or addr_p can be used to program the pmbus address. the pmbus address is a 7-bit code; 4msb bit is already fixed to 0100b. the mp2953b supports 8 addresses for up to 8 voltage regulator controllers or voltage rails by placing a 1% tolerance resistor (r top ) from the pin to 3.3v and a resistor (r bottom ) from the pin to ground. the pmbus ?all call? address is 00h. table 4 shows the resistor values for different pmbus addresses. table 4. pmbus address pmbus address r top (k ? ) 1% r bottom (k ? ) 1% 20h 3.32 0.0698 21h ns 0 22h 3.32 0.1 23h 3.32 0.178 24h 3.32 0.301 25h 3.32 0.422 26h 3.32 0.59 27h 2 0.976 vboot setup the boot voltage of the mp2953b can be set using either the pin or the register via the pmbus. to set using the pin, place a 1% tolerance resistor (r top ) from the pin to 3.3v and a resistor (r bottom ) from the pin to ground. table 5 shows 7 resistor values for the 7 boot voltage. table 5. boot voltage setting by pin vboot (v) r top (k ? ) 1% r bottom (k ? ) 1% 1.75 3.32 2.74 1.70 2 1.15 1.65 2 0.953 1.50 2 0.806 1.35 2 0.681 1.20 2 0.316 0 ns 0 to set using the pmbus, the boot voltage can support the entire vid table. switching frequency setup the switching frequency of mp2953b can be set using either the pin or the register via the pmbus. to set using the pin, a 1% tolerance resistor should be connected between vfs and ground. table 6 shows 9 resistor values for the 9 per- phase switching frequency. table 6. frequency setting by pin resistor (k ? ) 1% voltage (v) fs (khz)/phase 0 0 200 4.75 0.095 300 8.45 0.169 400 13.7 0.277 500 19.1 0.378 600 24.0 0.479 700 28.7 0.580 800 34.8 0.703 900 59 1.181 1000 to set using the pmbus, the switching frequency can be programmed from 200khz to 1mhz with 10khz step.
mp2953b ? digital pwm controller with pmbus for vr12.5 mp2953b rev. 1.01 www.monolithicpower.com 28 10/9/2015 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2015 mps. all rights reserved. pmbus commands command code command name type bytes default value data formats 01h operation r/w 1 80h direct 03h clear_faults send 0 - - 15h store_user_all send 0 - - 16h restare_user_all send 0 - - 21h vout_command r/w 2 007eh vid 24h vout_max r/w 2 00ffh vid 25h vout_margin_high r/w 2 0000h vid 26h vout_margin_low r/w 2 0000h vid 35h vin_on r/w 2 e850h linear 36h vin_off r/w 2 e848h linear 38h iout_cal_gain r/w 2 88a8h linear 39h iout_cal_offset r/w 2 f800h linear 55h vin_ov_fault_limit r/w 2 e870h linear 58h vin_uv_warn_limit r/w 2 e84ch linear 78h status_byte r 1 00h direct 79h status_word r 2 0000h direct 7ah status_vout r 1 00h vid 7bh status_iout r 1 00h direct 7ch status_ input r 1 00h direct 7dh status_ temperature r 1 00h direct 7eh status_ cml r 1 00h direct 88h read_vin r 2 e800h linear 89h read_iin r 2 e000h linear 8bh read_vout r 2 0000h vid 8ch read_iout r 2 f000h linear 8dh read_temperature r 2 0019h linear 96h read_pout r 2 0000h linear bah mfr_slope_slewrate_ ps2 r/w 2 01c1h direct bbh mfr_slope_cnt_ps2 r/w 2 03f0h direct d0h mfr_vr_config r/w 2 ec00h direct d1h mfr_temperature r/w 2 500ah direct d2h mfr_fs_set r/w 1 b2h direct d3h mfr_cur_gain r/w 2 0159h direct d4h mfr_ocp_set r/w 2 4525h direct d5h mfr_ovp_uvp_set r/w 2 4a54h direct d6h mfr_ocp_trg r/w 1 2ah direct d8h mfr_addr_pmbus r/w 1 8fh direct d9h mfr_addr_svid r/w 1 10h direct dbh mfr_otp_set r/w 2 961eh direct dch mfr_psi_trim r/w 2 0d8bh direct ddh mfr_cur_offset r/w 1 3ah direct e8h mfr_blank_time r/w 1 18h direct eah mfr_vboot r/w 2 017eh direct ebh mfr_icc_max r/w 1 ffh direct ech mfr_temp_max r/w 1 7dh direct edh mfr_sr r/w 2 1405h direct eeh mfr_vr_tolerance r/w 1 28h direct efh vendor_id_vr r/w 1 00h direct f0h product_id_vr r/w 1 00h direct
mp2953b ? digital pwm controller with pmbus for vr12.5 mp2953b rev. 1.01 www.monolithicpower.com 29 10/9/2015 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2015 mps. all rights reserved. pmbus commands (continued) command code command name type bytes default value data formats f1h product_rev_vr r/w 1 00h direct f2h mfr_configration_i d_lsb r/w 1 00h direct f3h mfr_configration_id_msb r/w 1 00h direct f4h protocol_id_vr r/w 1 00h direct f5h capability_vr r/w 1 7fh direct f7h mfr_plus_step r/w 1 22h vid fah mfr_slope_slewrate_ps0 r/w 2 00ech direct fbh mfr_slope_cnt_ps0 r/w 1 34h direct fch mfr_slope_cnt_ps1 r/w 2 020eh direct fdh mfr_slope_slewrate_ps1 r/w 2 01c9h direct feh mfr_protect_dis r/w 2 3100h direct
mp2953b ? digital pwm controller with pmbus for vr12.5 notice: the information in this document is subject to change wi thout notice. users should warra nt and guarantee that third party intellectual property rights are not infringed upon w hen integrating mps products into any application. mps will not assume any legal responsibility for any said applications. mp2953b rev.1.01 www.monolithicpower.com 30 10/9/2015 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2015 mps. all rights reserved. package information qfn-40 (5mmx5mm)

▲Up To Search▲

Price & Availability of MP2953BGU-0000-Z

	To Download MP2953BGU-0000-Z Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .